The invention relates generally to power modules and, more particularly, to low inductance power modules for high power electronic applications.
Modem power semiconductor switches, such as silicon Insulated Gate Bipolar Transistors (IGBTs), are capable of switching at much higher frequencies than earlier designs. Their lower switching losses enable new applications requiring high frequency power conversion. However, inherent to these faster switching transitions are problems associated with the high parasitic inductance of conventional packaging technologies. In particular, the voltage overshoot that occurs when a power device is switched off is proportional to the product of the parasitic inductance and the slope of the IGBT current during the switching. Because of the faster switching transitions of the new IGBTs, reducing the parasitic inductance is more critical for the new generation of power devices, to avoid excessive voltage overshoots when switching the devices off. For example, a converter operating at 500V DC bus with a 50 nH parasitic inductance and a relatively fast switching transition of 5 A/ns would lead to a 50% voltage overshoot.
A conventional power module with screw type power terminals is shown in FIG. 11. The parasitic inductance of conventional power modules is approximately 20 nH and the phase-leg inductance of conventional designs is typically in excess of 50 nH. The screw type power terminal leads contribute a large share of the parasitic inductance, with the remainder contributed by wire bonds and the layout of the substrates. In addition to their high parasitic inductance, the non-symmetric layouts result in poor current sharing between power devices. Accordingly, the use of conventional power modules with the new generation of fast IGBT devices undesirably leads to significantly higher electrical stresses.
There have been previous attempts to design a low inductance power module. For example, Mourick et al., “750 A, 75 V MOSFET Power Module with Sub-nH Inductance,” Sep. 2, 2002, IEEE, Proceedings of the 14th International Symposium on Power Semiconductor Devices and ICs, describe a low inductance multi-chip interconnect featuring a number of conductive webs that enable three-dimensional interleaving with power devices. During each switching transition, opposing magnetic fields are created by the currents through the power devices and by the currents in the conductive webs. The opposing magnetic fields cancel, resulting in a 2 nH parasitic inductance for the interconnect. However, Mourick et al. fail to address the design of a low parasitic inductance interconnect at the module and converter level. Other shortcomings of this design include the increased cost due to the addition of conductive webs, as well as the overall complexity of the module assembly.
U.S. Pat. No. 5,424,579, Arai et al., entitled “Semiconductor device having low floating inductance,” addresses device and substrate layout of a power module. However, Arai et al. feature a pair of conventional power terminals that keep the module inductance high. In addition, the layout is not symmetrical, which can lead to problems with dynamic and static current sharing between parallel power device die.
U.S. Pat. No. 5,574,312, Bayerer et al., entitled “Low-Inductance Power Semiconductor Module,” vaguely describes a low-inductance dual power module built on two-sides of a liquid-cooled heat sink, and there are several aspects of this design that make it impractical. For example, FIG. 2 of Bayerer et al. indicates an asymmetrical layout of the phase-leg, with devices on one side of the heat sink presumably mounted with collector/drain/cathode down, and with devices on the other side being flip-mounted with emitter/source/anode down. In addition, soldering of power devices to a double-sided heat sink is less practical and may require the use of multiple solders having different melting temperatures. Moreover, the module uses a mid-point power terminal to connect devices from one side of the heat sink to the other. This connection would invariably lead to high parasitic inductance, adding to the total phase-leg inductance.
It would therefore be desirable to develop a low inductance power module for use in packaging power devices. It would further be desirable to develop low inductance phase leg modules, and a modular three-phase inverter with low parasitic inductance. It would further be desirable to reduce the contribution to the parasitic inductance associated with the power terminal leads and to provide for static and dynamic current sharing between parallel power devices.